This invention concerns a MOS transistor that can be used to make high density integrated circuits.
FIG. 1 is a schematic diagram of the structure of a traditional MOS transistor. It shows an n channel MOS transistor. It is made on a type p solid silicon chip 1. Two sections 2 and 3 of type n+ are created, for example by ionic implantation, to form respectively the transistor""s source and drain. Reference 4 indicates the gate oxide film created on the surface of the chip 1 under which the sections 2 and 3 extend beyond. A gate electrode 5 is deposited on the gate oxide film 4. Source 6 and drain 7 electrodes are respectively created on sections 2 and 3 and the transistor is insulated from surrounding devices by an oxide film 8. The channel 9 is also shown, which is formed under the gate oxide film 4 when the transistor is correctly biased. The following important parameters are also shown in the diagram:
the channel length L,
the thickness of the gate oxide film d,
the depth of the junction rj.
The interest sustained in the development of high density integration, high frequency and low consumption silicon technologies is largely due to the new demands for portability, in particular for telecommunications and computer equipment. The exponential growth of technical and economic performances (according to Moore""s law) in silicon microelectronics is a strong indicator of the most impressive industrial progress of the twentieth century.
The widespread use of MOSFET transistors in the production of integrated circuits has enabled the density of integration to be increased significantly. However, the sustained growth in density of integration and performances of the electronics runs the risk of finding the physical limits of manufacturing. As an initial estimate, it is accepted that a reduction by a factor xcex1 in the length of a MOSFET transistor gate must also be accompanied by a simultaneous reduction by a factor xcex1 in the other characteristic dimensions (thickness of the gate oxide, width of channel, depth of junction), by a reduction by a factor xcex1 of the input voltage and an increase by a factor xcex1 in the doping concentration in the channel.
It is currently possible to obtain a minimum gate dimension of 22 nm. However, such a reduction implies modifications to the other characteristic dimensions of the transistor, which are impossible to achieve either now or in the near future, according to xe2x80x9cThe International Technology Roadmap for Semiconductorsxe2x80x94ITRSxe2x80x9d, 1999, SIA Semiconductor Industry Association.
The technological barriers preventing the manufacture of a traditional MOS transistor with a gate length of 22 nm are in particular as follows:
I): very shallow extension from the source and drain to their junction with the channel (from 8 to 13 nm);
II): an extremely abrupt concentration gradient at the source/channel and drain/channel junctions (0.5 nm/dec.);
III): a very thin film of silicon (12 nm);
IV): lower consumption of silicon during silicide coating reaction (from 7 to 17 nm);
V) : low resistance by silicon square due to its reduced thickness (12.5 xcexa9/for a thickness of silicon of 12 nm);
VI): a very low specific drain and source contact resistance at the siliconxe2x80x94silicide interface (less than 1.5 10xe2x88x928 xcexa9/cm2);
VII): a very high level of doping in the channel (3xc3x971019 cm3).
The miniaturisation of MOS devices requires shorter and shorter junctions to be formed, which makes optimising the specific contact resistance extremely difficult. The reduction of this resistance is usually achieved by a silicide deposition process, which permits an alloy to be obtained with low resistance at the silicidexe2x80x94silicon interface, for example the TiS2/Si and CoSi2/Si interfaces. However, the reaction of the silicide deposition process leads to a consumption of silicon which can lead, on the one hand, to a reduction of the effective contact surface and, on the other hand, to an increase in the specific contact resistance given that the silicidexe2x80x94silicon interface values are too low.
The article xe2x80x9cProposal of a SCHOTTKY barrier SET Aiming at a Future Integrated Devicexe2x80x9d by FUJISHIMA et al., published in the IEICE Transactions on Electronics, JP Institute of Electronics Information and Comm. Eng. Tokyo, vol. E 80-C, noxc2x07, Jul. 1st, 1997, pages 881 to 885, reveals a one electron MOS transistor. This device uses the Coulomb effect, which is to say a load quantification effect, which allows the current to be oscillated according to the gate voltage applied. Several constraints are imposed in this case. The transistor must operate at low temperature (e.g. 10 K) so that the load quantification is not masked by the load temperature fluctuations. It is formed by a silicon channel whose external connection (source and drain contacts) passes via the Schottky barriers, which act as a tunnel barrier. In order to use the Coulomb blocking effect, the tunnel resistance of the Schottky barriers must be greater than the resistance quantum. This constraint justifies the use of relatively high Schottky barriers. Finally, the device described in this article is a quantum wire on non-doped silicon, which means that the width of the device is significantly reduced. This very narrow width is essential for the operation of the SET transistor in order to reduce all of the capacities between the transistor terminal contacts and the silicon channel, as the Coulomb blockage can only be achieved if very low capacities are used. The very narrow width of the device allows a relatively high junction tunnel resistance to be obtained, as the resistance is inversely proportional to the emission surface.
This invention allows the problems of manufacturing MOS transistors for high density integrated circuits to be overcome.
It concerns a MOS transistor made in the thin film of silicon of an SOI chip, said thin film being slightly doped and of less than 30 nm in thickness, the source and drain contacts being of the Schottky type at the lowest level of Schottky barrier possible for majority carriers, with an accumulation type transistor operation.
In preference, the level of doping of the thin film is between 5xc3x971014 cmxe2x88x923 and 1017 cmxe2x88x923. Advantageously, it is of around 1015 cmxe2x88x923, for example 1 or 2xc3x971015 cmxe2x88x923.
If the thin film is p doped, to obtain a p-MOSFET, the source and drain contacts are advantageously composed of a PtGeSi silicide. Annealing, for example at a temperature of around 600xc2x0 C. for approximately 10 minutes, permits the Schottky barrier of these contacts to be lowered.
If the thin film is n doped to obtain an n-MOSFET, the source and drain contacts can be composed of an erbium based silicide.